CVE-2026-98546
Microsoft — arm64/boot: Disable trapping of PMZR_EL0 writes to EL2
Microsoft · Not classified by connected sources
EVRS 0 of 100 Informational
Monitor
Rank 2,843 of 2,960 tracked
Why it scores 0
Evidence available: 2 of 8 signalsNo strong exploitation, disclosure, or severity signal is available for this CVE yet.
- CISA KEVDid not apply
- RansomwareNo data
- Vendor exploitationNo data
- EPSSDid not apply
- Microsoft Exploitability IndexNo data
- Pre-patch disclosureNo data
- KEV recencyNo data
- CVSSNo data
The band answers “how soon”, not “how bad”. No data for: Ransomware, Vendor exploitation, Microsoft Exploitability Index, Pre-patch disclosure, KEV recency, CVSS. Why some signals show no data
Fix
No fixed version identified yetAffected versions
Not identified by the connected sources
Remediation
NVD lists one or more references for this CVE that aren't tagged as a patch or vendor advisory. Review them directly to confirm patch availability and applicability before making a remediation decision.
Evidence
Each value with its source| Measure | Value | Source |
|---|---|---|
| CVSS base scoreHow severe the flaw is in itself. It does not say how likely an attack is. | Not publishedNVD and the CVE record were checked and hold no score. | NVD |
| FIRST EPSSFIRST's estimate of the chance this is exploited in the next 30 days, and how that ranks against all CVEs. | 0.002 (9.3rd pctl) | FIRST EPSS |
| Actively exploitedWhether a source of record has confirmed attacks using it in the wild. | Not confirmed | Patch Tuesday |
| Public exploit moduleA module existing is not the same as active exploitation. | None known | Metasploit |
| EUVD cross-referenceENISA's record: CVSS 0.0, assigned by Linux. | Listed | ENISA EUVD |
Description
NVDIn the Linux kernel, the following vulnerability has been resolved: arm64/boot: Disable trapping of PMZR_EL0 writes to EL2 __init_el2_fgt2() writes one mask to both HDFGRTR2_EL2 and HDFGWTR2_EL2. PMZR_EL0 is write-only, so its trap bit, nPMZR_EL0, exists only in HDFGWTR2_EL2 and is therefore never set: a PMZR_EL0 write from the host traps to EL2, where the nVHE hypervisor has no handler and BUG()s. The kernel never writes PMZR_EL0, but kernel.perf_user_access=1 has the PMU driver set PMUSERENR_EL0.UEN for a task with a user-read event, so a write from EL0 reaches the trap and takes the host down without a panic message. Accumulate the HDFGWTR2_EL2 bits separately, as __init_el2_fgt() already does for HDFGWTR_EL2, and set nPMZR_EL0 with the other FEAT_PMUv3p9 bits.